This invention relates to a line memory of simple delay type which stores serial data, converting them into parallel data.
In these days, requirement for high-density integrated circuit using a semiconductor has been increased. As elements of large-sized integrated circuit for a specific purpose, ROM, RAM and the like which are conventionally provided outside are built in one integrated circuit, in addition to AND element and OR element, the integration of which almost reaches to a physical limit. The semiconductor integrated circuit in which such high-density functions are built in one part becomes necessary in various fields of article, such as portable compact devices.
There is a line memory as an example of function device, such as ROH, RAM, which are provided outside. The line memory is a device having an advanced function for a device dealing with data having periodicity, such as image information. While the line memory enhances the integration of elements by bearing a data holding function to the RAM, much time is required for memory access, thus the RAM bars high-speed operation. External serial data are converted into parallel data by using the internal device, such as a shift register to thus enable the high-speed operation apparently.
There are three types of line memories according to the function: (1) simple delay type, (2) START type and (3) write/read clock type. In the simple delay type, data are written in synchronization with a clock after a reset signal is initially input, then the data are read out after a given delay time.
In the conventional simple delay method, only serial data whose number is equal to the serial/parallel number (=number of serial data to be converted into parallel data, i.e., the number of data composing one parallel data) are converted into parallel data to thus access the parallel data to a memory. Thereafter, the parallel data are converted into serial data. The memory access of the parallel data is an operation of writing one parallel data into one array of memory, and the access is repeated times of number of arrays in the memory array. Accordingly, the delay amount in the simple delay method is the serial/parallel number.times.the array number of memory array.
However, in the line memory of above mentioned simple delay type, as for data having an arbitrary bit width that fraction bits remains when the bit width is divided by the serial/parallel number, the remainder bits are not positioned at a head of one parallel data when the remainder bits are output from the serial/parallel converter though the remainder bits are parallel-converted by a shift register or the like, because the parallel operation is performed in the line memory. Therefore, the delay amount in the simple delay method is restricted to the serial/parallel number.times.the array number of memory array, with a result that the line memory of simple delay type is applicable only to data of bit width which agrees the restriction. In consequence, the use of line memory of simple delay type is so restricted.
Recently, a case is desired that, when an image is formed by indicating data written in the line memory onto a display of a Braun tube, almost part of the Braun tube continues to display a previous image and remaining small part displays new image different from the previous image. However, since the parallel operation is performed in the line memory, there is a restriction that control to data is performed per one parallel operation. Therefore, the conventional line memory is hard to perform the control that is capable of writing of only arbitrary data.